High density memory devices, for example DRAMs, require relatively long access times to retrieve information bits from a specified location. For example as the number of memory cells per device increases, as for example from 32K bits to 64K bits to 1M bits and beyond, the required access time becomes longer and the individual access time becomes more critical due to the increased number of accesses required from a large memory device. In the prior art, cache memory systems have been developed to store segments of the information from a large memory device or system used in mainframes or minicomputers into a smaller faster memory device or system which has faster access time. Then, to retrieve a specific information bit which is located in the cache memory, requires a short access time, while an information bit not located in the cache memory requires a longer time to access from the main memory device.
However, cache memory systems have, heretofore, been seldom applied to microcomputer systems or to single chip memory arrays for several reasons. Firstly, the memory capacity of main memories in these devices was not sufficiently large to warrant cache memory use. Further, control of cache memory systems was felt to require unjustified occupation of processor capabilities in smaller systems. Further, the employment of cache memory systems was not flexible enough for employment in the microcomputer environment. Further, use of cache memory was too costly for the benefit in speed which their use provided to microcomputer systems.